Çѱ¹Á¤º¸Åë½ÅÇÐȸ ³í¹®Áö (Journal of the Korea Institute of Information and Communication Engineering)
Current Result Document :
ÇѱÛÁ¦¸ñ(Korean Title) |
CABAC ºÎȣȱ⸦ À§ÇÑ °í¼Ó ÀÌÁø »ê¼ú ºÎȣȱâÀÇ ¼³°è |
¿µ¹®Á¦¸ñ(English Title) |
Design of High Speed Binary Arithmetic Encoder for CABAC Encoder |
ÀúÀÚ(Author) |
¹Ú½Â¿ë
Á¶Çö±¸
·ù±¤±â
Seungyong Park
Hyungu Jo
Kwangki Ryoo
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¿ø¹®¼ö·Ïó(Citation) |
VOL 21 NO. 04 PP. 0774 ~ 0780 (2017. 04) |
Çѱ۳»¿ë (Korean Abstract) |
º» ³í¹®Àº HEVCÀÇ ¿£Æ®·ÎÇÇ ÄÚµù¹æ¹ýÀÎ CABAC ºÎȣȱ⸦ À§ÇÑ È¿À²ÀûÀÎ ÀÌÁø »ê¼ú ºÎȣȱâ Çϵå¿þ¾î ±¸Á¶¸¦ Á¦¾ÈÇÑ´Ù. CABACÀº HEVC Ç¥ÁØ¿¡¼ »ç¿ëµÇ´Â ¿£Æ®·ÎÇÇ ÄÚµù ¹æ¹ýÀ¸·Î Åë°èÀû Áߺ¹¼ºÀ» Á¦°ÅÇÏ¿© ¿µ»óÀÇ ³ôÀº ¾ÐÃà·üÀ» Áö¿øÇÑ´Ù. ÇÏÁö¸¸ ÀÌÁø »ê¼ú ºÎÈ£È(Binary Arithmetic Encode)´Â µ¥ÀÌÅÍ °£ÀÇ ÀÇÁ¸ °ü°è°¡ ³ô¾Æ º´·Ä󸮰¡ ¾î·Æ°í ½Ç½Ã°£ ó¸®ÀÇ Áö¿¬ÀÌ ¹ß»ý µÈ´Ù. Á¦¾ÈÇÏ´Â ÀÌÁø »ê¼ú ºÎȣȱâ´Â ÀÔ·ÂÀ¸·Î µé¾î¿À´Â ºóÀ» °í¼ÓÀ¸·Î ó¸®Çϱâ À§ÇÏ¿© ÀçÁ¤±ÔÈ °úÁ¤À» ºÐ¸® ½ÃÄÑ µ¿ÀÛÇϵµ·Ï ¼³°èÇÑ´Ù. ±âÁ¸ÀÇ ¹Ýº¹ÀûÀÎ ¾Ë°í¸®ÁòÀ» º´·ÄÀûÀ¸·Î ó¸®ÇÔÀ¸·Î½á ÃÖ´ëÁö¿¬½Ã°£(Critical Path)À» ÃÖÀûÀ¸·Î ÁÙÀÏ ¼ö ÀÖ´Â 4´Ü°èÀÇ ÆÄÀÌÇÁ¶óÀÎ ±¸Á¶·Î ¼³°èÇÏ¿´´Ù. ¶ÇÇÑ, ¸ÖƼ-ºó ±¸Á¶¸¦ Àû¿ëÇÏ¿© Ŭ·Ï »çÀÌŬ ´ç 3°³ÀÇ ºóÀ» ó¸®ÇÑ´Ù. Á¦¾ÈÇÏ´Â CABACÀÇ ÀÌÁø »ê¼ú ºÎȣȱâ´Â Verilog-HDL·Î ¼³°èÇÏ¿´À¸¸ç 65nm °øÁ¤À¸·Î ÇÕ¼ºÇÏ¿´´Ù. ÇÕ¼º °á°ú °ÔÀÌÆ®¼ö´Â 8.07K À̸ç ÃÖ´ë µ¿ÀÛÁÖÆļö´Â 769MHz·Î ÃÖ´ë ºó 󸮷®Àº 2307Mbin/sÀÌ´Ù. Á¦¾ÈÇÏ´Â Çϵå¿þ¾î ±¸Á¶´Â ±âÁ¸ÀÇ ÀÌÁø »ê¼ú ºÎȣȱâ¿Í ºñ±³ÇÏ¿© ÃÖ´ë ºó 󸮷®ÀÌ 26%¸¸Å Áõ°¡ ÇÏ¿´´Ù.
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¿µ¹®³»¿ë (English Abstract) |
This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC encoding, which is an entropy coding method of HEVC. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 8.07K and maximum operating speed of 769MHz. It processes the four bin per clock cycle. Maximum processing speed increased by 26% from existing hardware architectures.
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Å°¿öµå(Keyword) |
H.264/AVC
HEVC
CABAC
ÀÌÁø »ê¼ú ºÎȣȱâ
¿£Æ®·ÎÇÇ ÄÚµù
H.264/AVC
HEVC
CABAC
Binary Arithmetic Encoder
Entropy Coding
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ÆÄÀÏ÷ºÎ |
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